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| SL74HC4053 Analog Multiplexer/Demultiplexer High-Performance Silicon-Gate CMOS The SL74HC4053 utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE). The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input.When the Enable pin is high, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. * Fast Switching and Propagation Speeds * Low Crosstalk Between Switches * Diode Protection on All Inputs/Outputs * Analog Power Supply Range (VCC-VEE)=2.0 to 12.0 V * Digital (Control) Power Supply Range (VCC-GND)=2.0 to 6.0 V * Low Noise ORDERING INFORMATION SL74HC4053N Plastic SL74HC4053D SOIC TA = -55 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM Triple Single-Pole, Double-Position Plus Common Off FUNCTION TABLE Control Inputs Enable C L L L L PIN 16 =VCC PIN 7 = VEE PIN 8 = GND L L L L H L L L L H H H H X Select B L L H H L L H H X A L H L H L H L H X Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 None X0 X1 X0 X1 X0 X1 X0 X1 ON Channels X = don't care SLS System Logic Semiconductor SL74HC4053 MAXIMUM RATINGS * Symbol VCC VEE VIS VIN I PD Tstg TL * Parameter Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE) Negative DC Supply Voltage (Referenced to GND) Analog Input Voltage Digital Input Voltage (Referenced to GND) DC Input Current Into or Out of Any Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to +14.0 -7.0 to +0.5 VEE - 0.5 to VCC+0.5 -1.5 to VCC +1.5 25 750 500 -65 to +150 260 Unit V V V V mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VEE VIS VIN VIO * Parameter Positive Supply Voltage (Referenced to GND) (Referenced to VEE) Negative DC Supply Voltage (Referenced to GND) Analog Input Voltage Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch Operating Temperature, All Package Types Input Rise and Fall Time (Channel Select or Enable Inputs) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 2.0 - 6.0 VEE GND -55 0 0 0 Max 6.0 12.0 GND VCC VCC 1.2 +125 1000 500 400 Unit V V V V V C ns TA tr, t f * For voltage drops across the switch greater than 1.2 V (switch on), excessive V current may be drawn; CC i. e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range indicated in the Recommended Operating Conditions.. Unused digital input pins must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused Analog I/O pins may be left open or terminated. SLS System Logic Semiconductor SL74HC4053 DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE=GND, Except Where Noted VCC Symbol VIH Parameter Minimum High-Level Input Voltage, ChannelSelect or Enable Inputs Maximum Low -Level Input Voltage, ChannelSelect or Enable Inputs Maximum Input Leakage Current, Channel-Select or Enable Inputs Maximum Quiescent Supply Current (per Package) Test Conditions RON = Per Spec V 2.0 4.5 6.0 2.0 4.5 6.0 6.0 Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.3 0.9 1.2 0.1 85 C 1.5 3.15 4.2 0.3 0.9 1.2 1.0 125 C 1.5 3.15 4.2 0.3 0.9 1.2 1.0 Unit V VIL RON = Per Spec V IIN VIN=VCC or GND, VEE=-6.0 V A ICC Channel Select = VCC or GND Enable = VCC or GND VIS = VCC or GND VIO= 0 V VEE = GND VEE = -6.0 A 6.0 6.0 2 8 20 80 40 160 DC ELECTRICAL CHARACTERISTICS Analog Section VCC Symbol Parameter Test Conditions V VEE V Guaranteed Limit 25 C to -55C 190 120 100 150 100 80 30 12 10 0.1 85 C 240 150 125 190 125 100 35 15 12 0.5 125 C 280 170 140 230 140 115 40 18 14 1.0 Unit RON Maximum "ON" Resistance VIN=VIL or VIH VIS = VCC or VEE IS 2.0 mA(Figure 1) VIN=VIL or VIH VIS = VCC or VEE (Endpoints) IS 2.0 mA(Figure 1) 4.5 4.5 6.0 4.5 4.5 6.0 4.5 4.5 6.0 6.0 0.0 -4.5 -6.0 0.0 -4.5 -6.0 0.0 -4.5 -6.0 -6.0 RON Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Maximum Off- Channel Leakage Current, Any One Channel Maximum Off- Channel Leakage Current, Common Channel VIN=VIL or VIH VIS = 1/2 (VCC- VEE) IS 2.0 mA VIN=VIL or VIH VIO = VCC- VEE Switch Off (Figure 2) VIN=VIL or VIH VIO= VCC- VEE Switch Off (Figure 3) VIN=VIL or VIH Switch to Switch = VCC- VEE (Figure 5) IOFF A 6.0 -6.0 0.1 1.0 2.0 ION Maximum On- Channel Leakage Current, Channel to Channel 6.0 -6.0 0.1 1.0 2.0 A SLS System Logic Semiconductor SL74HC4053 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input t r=t f=6.0 ns) VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Channel-Select to Analog Output (Figures 8 and 9) Maximum Propagation Delay , Analog Input to Analog Output (Figures 10 and 11) Maximum Propagation Delay , Enable to Analog Output (Figures 12 and 13) Maximum Propagation Delay , Enable to Analog Output (Figures 12 and 13) Maximum Input Capacitance, Channel-Select or Enable Inputs Maximum Capacitance Analog I/O Common O/I Feedthrough Power Dissipation Capacitance (Per Package) (Figure 15) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC All Switches Off 50 1.0 50 1.0 50 1.0 V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit 25 C to -55C 370 74 63 60 12 10 290 58 49 345 69 59 10 35 85C 465 93 79 75 15 13 364 73 62 435 87 74 10 35 125C 550 110 94 90 18 15 430 86 73 515 103 87 10 35 Unit ns tPLH, t PHL ns tPLZ, t PHZ ns tPZL, t PZH ns CIN CI/O pF pF Typical @25C,VCC=5.0 V, VEE=0 V 45 pF SLS System Logic Semiconductor SL74HC4053 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V) VCC Symbol BW Parameter Maximum OnChannel Bandwidth or Minimum Frequency Response (Figure 5) Off-Channel Feedthrough Isolation (Figure 6) Test Conditions fin=1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequence Until dB Meter Reads -3 dB RL =50 , CL=10 pF V VEE V Limit* 25 C Unit MHz 2.25 4.50 6.00 -2.25 -4.50 -6.00 120 120 120 - fin= Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL =600 , CL=50 pF fin = 1.0 MHz, RL =50 , CL=10 pF dB 2.25 4.50 6.00 2.25 4.50 6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -50 -50 -50 -40 -40 -40 mVpp - Feedthrough Noise, Channel Select Input to Common O/I (Figure 7) VIN 1 MHz Square Wave (t r = t f = 6 ns) Adjust RL at Setup so that IS= 0 A Enable = GND RL =600 , CL=50 pF 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 2.25 4.50 6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 -2.25 -4.50 -6.00 25 105 135 35 145 190 dB -50 -50 -50 -60 -60 -60 % RL =10 , CL=10 pF - Crosstalk Between Any Two Switches (Figure 14) fin= Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL =600 , CL=50 pF fin = 1 MHz, RL =50 , CL=10 pF THD Total Harmonic Distortion (Figure 16) fin= 1 kHz, RL =10 k, CL=50 pF THD = THDMeasured - THDSource VIS =4.0 VPP sine wave VIS =8.0 VPP sine wave VIS =11.0 VPP sine wave 2.25 4.50 6.00 -2.25 -4.50 -6.00 0.10 0.08 0.05 * Limits not tested. Determined by design and verified by qualification. SLS System Logic Semiconductor SL74HC4053 Figure 1. On Resistance Test Set-Up Figure 2. Maximum Off Channel Leakage Current, Any One Channel, Test Set-UP Figure 3. Maximum Off Channel Leakage Current, Common Channel, Test Set-UP * Includes all probe and jig capacitance. Figure 4. Maximum On Channel Leakage Current, Channel to Channel, Test Set-UP Figure 5. Maximum On Channel Bandwidth, Test Set-UP * Includes all probe and jig capacitance. Figure 6. Off Channel Feedthrough Isolation, Test Set-UP * Includes all probe and jig capacitance. Figure 7.Feedthrough Noise, Channel Select to Common Out, Test Set-UP System Logic Semiconductor SLS SL74HC4053 * Includes all probe and jig capacitance. Figure 8. Swi tching Weveforms Figure 9. Test Set-UP, Channel Select to Analog Out * Includes all probe and jig capacitance. Figure 10. Switching Weveforms Figure 11. Test Set-UP, Analog In to Analog Out Figure 12. Switching Weveforms Figure 13. Test Set-UP, Enable to Analog Out SLS System Logic Semiconductor SL74HC4053 * Includes all probe and jig capacitance. Figure 14. Crosstalk Between Any Two Switches, Test Set-Up Figure 15. Power Dissipation Capacitance, Test Set-Up Figure 16. Total Harmonic Distortion, Test Set-UP EXPANDED LOGIC DIAGRAM SLS System Logic Semiconductor |
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